The present invention relates to an electrically erasable and programmable read-only non-volatile memory (EEPROM) cell or, more specifically, a flash EEPROM. The present invention also relates to a memory array containing a plurality of such EEPROM cells arranged in a matrix of rows and columns of such memory cells.
One prior art flash memory device is a stack gate flash EEPROM where a single stack-gate transistor constitutes the memory cell. It programs as a traditional UV-erasable EPROM, using the mechanism of hot-electron injection to a floating gate, and erases through Fowler-Nordheim tunneling mechanism from the floating gate to the source region. Such device suffers the disadvantages of (1) over-erase sensitivity, where the memory cell can be erased to a negative threshold voltage thus rendering the cell in a conductive state even when the gate of the cell is deselected and biased at a ground potential, and (2) high programming current, which requires the memory cell to be programmed by a separate power supply voltage. See for example, U.S. Pat. No. 4,698,787.
A second type of flash memory device utilizes a split gate configuration. This eliminates the over-erase sensitivity, because even if the floating gate is over-erased, conduction in the channel requires the biasing of the control gate which is over another portion of the channel. However, the programming and erase mechanisms are the same as the stack-gate configuration. The disadvantage of this configuration is that it increases the cell size and can suffer an alignment sensitivity because of the split gate arrangement. See for example, U.S. Pat. No. 5,029,130.
Yet another type of flash memory cell utilizes the so called source-side injection technique which minimizes the hot electron programming current to the extent that an on-chip voltage multiplier can be used to provide sufficient programming current from a single 5 or 3.3 V power supply. However, the structure of these cells can still suffer from (1) alignment sensitivity, (2) poor scalability and (3) compromise between cell size and coupling ratio. See U.S. Pat. No. 5,194,925.
U.S. Pat. Nos. 5,303,187, 4,462,090 and 5,280,446 disclose a single transistor memory cell having four terminals with a select gate, a control gate, a source and a drain. The memory cell disclosed in U.S. Pat. No. 5,303,187, however, erases by tunneling of electrons from a floating gate to the substrate (see Col. 5, line 64-68). This is undesirable because of the lower coupling ratio, due to the large capacitance between the floating gate and the substrate. As a result, a higher voltage to erase is required. In addition, it requires a negative voltage to supply the potential for erase operation of an n-type cell. This requires the process to provide a high PMOS junction breakdown voltage, and a high field isolation threshold voltage and a low PMOS transistor body effect so that the circuit can provide a negative voltage of sufficient magnitude to achieve the necessary erase operation.
Each of U.S. Pat. Nos. 4,462,090 and 5,280,446 discloses a split gate configuration for the select gate. Such a split gate configuration for the select gate can cause punch through sensitivity due to misalignment.
Lastly, U.S. Pat. No. 5,338,952 discloses a split gate memory cell with a floating gate formed as a spacer that is disposed adjacent the select gate and underneath the control gate. With this configuration, however, there is an insufficient amount of capacitive coupling between the floating gate and the control gate.
The present invention is an electrically erasable and programmable memory device that includes a substrate of semiconductor material of a first conductivity type, spaced-apart first and second regions formed in the substrate and having a second conductivity type different from the first conductivity type, with a channel region therebetween, a conductive select gate formed over and insulated from the substrate with the select gate extending over a first portion of the channel, and conductive floating and control gates. The floating gate is formed as a spacer over and insulated from the substrate, and includes a bottom surface extending over a second portion of the channel region, and first and second side surfaces extending from the bottom surface. The control gate is formed over and insulated from the floating gate, and includes a first portion disposed adjacent to the first floating gate side surface, and a second portion disposed adjacent to the second floating gate side surface.
In another aspect of the present invention, a method of making a memory device on a semiconductor substrate of a first conductivity type includes the steps of forming spaced-apart first and second regions in the substrate that have a second conductivity type different from the first conductivity type, wherein a channel region is defined in the substrate between the first and second regions, forming a conductive select gate over and insulated from the substrate, wherein the select gate extends over a first portion of the channel and has a first height, forming a conductive floating gate spacer over and insulated from the substrate, and forming a conductive control gate over and insulated from the floating gate. The floating gate includes a bottom surface extending over a second portion of the channel region, and first and second side surfaces extending from the bottom surface to a height greater than the first height. The control gate includes a first portion disposed adjacent to the first floating gate side surface and a second portion disposed adjacent to the second floating gate side surface.
In yet another aspect of the present invention, a method of making a memory device on a semiconductor substrate of a first conductivity type includes the steps of forming spaced-apart first and second regions in the substrate that have a second conductivity type different from the first conductivity type, wherein a channel region is defined in the substrate between the first and second regions, forming a first layer of insulating material on substrate, forming a select gate on the first insulating layer, wherein the select gate is positioned over a first portion of said channel, forming a second layer of insulating material on the select gate, forming a layer of material on the second layer of insulating material, forming a floating gate spacer of conductive material adjacent to and insulated from the select gate and adjacent to the layer of material, removing the layer of material, and forming a conductive control gate over and insulated from the floating gate and over the second insulating layer. The floating gate includes a bottom surface extending over a second portion of the channel region, and first and second side surfaces extending from the bottom surface. The control gate includes a first portion disposed adjacent to and insulated from the first floating gate side surface and a second portion disposed adjacent to and insulated from the second floating gate side surface.
In still yet another aspect of the present invention, a method of designing an electrically erasable and programmable memory device formed on a substrate of semiconductor material of a first conductivity type is used to form a device that includes spaced-apart first and second regions formed in the substrate with a second conductivity type different from the first conductivity type and with a channel region therebetween, a conductive select gate formed over and insulated from the substrate and extending over a first portion of the channel, a conductive floating gate formed as a spacer over and insulated from the substrate and having a bottom surface extending over a second portion of the channel region and first and second side surfaces extending from the bottom surface, and a conductive control gate formed over and insulated from the floating gate with a first portion disposed adjacent to the first floating gate side surface and a second portion disposed adjacent to the second floating gate side surface. The improvement steps include selecting a desired capacitive coupling ratio between the floating gate and the control gate and adjusting a height of the control gate second portion to achieve the desired capacitive coupling ratio.
In yet one more aspect of the present invention, an electrically erasable and programmable memory device includes a substrate of semiconductor material of a first conductivity type, spaced-apart first and second regions formed in the substrate and having a second conductivity type different from the first conductivity type, with a channel region therebetween, a conductive select gate formed over and insulated from the substrate, the select gate extending over a first portion of the channel, a conductive floating gate formed as a spacer over and insulated from the substrate, and a conductive control gate formed over and insulated from the floating gate. The floating gate includes a bottom surface extending over a second portion of the channel region, and first and second side surfaces extending from the bottom surface. The control gate includes a first portion disposed adjacent to the first floating gate side surface, and a second portion disposed adjacent to the second floating gate side surface. The control gate is formed by the process of selecting a desired capacitive coupling ratio between the floating gate and the control gate, and forming the control gate second portion with a predetermined height for achieving the desired capacitive coupling ratio.
Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.